The present invention relates to a power device that utilizes a silicon carbide substrate (SiC substrate) used to handle high voltages and high currents.
Conventionally, a power device has been desired to be low-loss since it is a semiconductor device that handles high voltages and high currents. In the prior art, a power device that uses a silicon (Si) substrate has been the prevailing device. However, in recent years, a power device that uses a SiC (silicon carbide) substrate made of a semiconductor material containing Si and C in the ratio 1:1 is getting attention and being developed. Since the dielectric breakdown field of SiC is ten times greater than that of silicon, SiC makes it possible to maintain high reverse blocking voltage even if a depletion layer at a pn junction or a Schottky junction is thinned. Therefore, if a SiC substrate is used, the thickness of the resulting device can be reduced, and dopant concentration can be increased. Accordingly, a SiC substrate is highly expected as a substrate material for forming a power device that has a low on-state resistance, handles high voltages, and achieves low power loss. Herein, SiC substrates include a substrate which is made of a material different from SiC and on which a SiC crystal layer is epitaxially grown. Silicon carbide represented by “SiC” is a material whose physical and chemical properties are different from those of silicon that is represented by “Si:C” and contains a small amount (a few percent or less) of C.
However, the carrier mobility of a MISFET that uses a SiC substrate, in a channel region, is disadvantageously lower that that of a MISFET that uses a silicon substrate. This is because a thermal oxide film on a silicon substrate is made of pure silicon oxide, whereas carbon remains in a thermal oxide film on a SiC substrate, and the interface state density at an interface between the thermal oxide film and a SiC layer (semiconductor layer) is high.
Therefore, in order to overcome this disadvantage, an accumulation-mode MISFET is recently proposed as a MISFET that uses a SiC substrate, instead of a normal inversion-mode MISFET. For example, as such an accumulation-mode MISFET that uses a SiC substrate, Document 1 (Japanese Unexamined Patent Publication No. 2001-144288 (pp. 3-7, FIGS. 5 through 10)) discloses a double-implantation MISFET in which a channel layer at a surface region is epitaxially grown.
FIG. 14 is a cross-sectional view illustrating the structure of a conventional accumulation-mode MISFET that uses a SiC substrate, i.e., a conventional double-implantation MISFET.
As shown in FIG. 14, the double-implantation MISFET includes: a SiC substrate 131; a high resistance SiC layer 132 provided on the SiC substrate 131; a p-well region 133 formed by implanting p-type dopant ions into a part of a surface region of the high resistance SiC layer 132; a channel layer 135 formed on upper surfaces of the p-well region 133 and the high resistance SiC layer 132 and containing n-type dopant; a source region 136 formed by implanting n-type dopant ions into parts of the channel layer 135 and the p-well region 133; a gate insulating film 137 formed of a thermal oxide film provided on a surface of the channel layer 135; a gate electrode 110 provided on the gate insulating film 137; a source electrode 138 that is provided on a wall surface of a groove passing through the source region 136 to reach the p-well region 133, and that is formed so as to be in contact with the p-well region 133 and the source region 136; and a drain electrode 139 formed so as to be in ohmic contact with the backside of the SiC substrate 131.
The source region 136 and the high resistance SiC layer 132, each being an n-type semiconductor layer, are electrically connected with each other via the channel layer 135 that is also an n-type semiconductor layer. Furthermore, a portion of the channel layer 135 located in an upper part of the source region 136 is partially removed. The source electrode 138, the source region 136 and the p-well region 133 are annealed so that they are in ohmic contact with each other. The SiC substrate 131 and the drain electrode 139 are in ohmic contact with each other.
FIGS. 15A through 15E and FIGS. 16A through 16E are cross-sectional views illustrating process steps for fabricating a conventional double-implantation MISFET.
First, in the step shown in FIG. 15A, on a low resistance SiC substrate 131, a high resistance SiC layer 132 whose resistance is higher than that of the SiC substrate 131 (and whose dopant concentration is low) is epitaxially grown.
Next, in the step shown in FIG. 15B, p-type dopant ions are selectively implanted into a part of a surface region of the high resistance SiC layer 132, thereby forming a p-well region 133.
Then, in the step shown in FIG. 15C, annealing for activating the dopants that have been implanted thus far is performed. At this time, a surface of the p-well region 133 becomes rough.
Subsequently, in the step shown in FIG. 15D, a channel layer 135 containing an n-type dopant is epitaxially grown on the surfaces of the p-well region 133 and the high resistance SiC layer 132.
Thereafter, in the step shown in FIG. 15E, high concentration n-type dopant ions are implanted into parts of the channel layer 135 and the p-well region 133, thus forming a source region 136 that passes through the channel layer 135 to reach an inner portion of the p-well region 133. In this case, the source region 136 and the high resistance SiC layer 132, each being an n-type semiconductor layer, are electrically connected via the channel layer 135 that is also an n-type semiconductor layer.
Next, in the step shown in FIG. 16A, annealing for activating the dopant implanted into the source region 136 is performed. At this time, surfaces of the channel layer 135 and the source region 136 become rough.
Then, in the step shown in FIG. 16B, a groove 134 that passes through the source region 136 to reach an upper portion of the p-well region 133 is formed, and then exposed surfaces of the channel layer 135, the source region 136 and the p-well region 133 are thermally oxidized, thus providing a gate insulating film 137 formed of a thermal oxide film.
Subsequently, in the step shown in 16C, portions of the gate insulating film 137 located on a wall surface of the groove 134 and around the groove 134 are removed.
Thereafter, in the step shown in FIG. 16D, a source electrode 138 is formed on an exposed portion of the source region 136 from which the gate insulating film 137 has been removed. Further, a drain electrode 139 is formed on the backside of the SiC substrate 131.
Next, in the step shown in FIG. 16E, a gate electrode 110 is formed on the gate insulating film 137. Furthermore, annealing is performed so that the source electrode 138, the source region 136 and the p-well region 133 are in ohmic contact with each other, and the SiC substrate 131 and the drain electrode 139 are in ohmic contact with each other.
In the conventional MISFET that uses the SiC substrate, the channel layer 135, the source region 136 and the high resistance SiC layer 132 are each formed by an n-type semiconductor layer; therefore, this MISFET is not an inversion-mode MISFET (i.e., a typical MISFET) that utilizes inversion of the channel layer, but an accumulation-mode MISFET that utilizes an accumulation state of the channel layer. In an accumulation-mode MISFET having such a channel layer, as compared with an inversion-mode MISFET, electric current flows to a deep region separated from an MIS interface; therefore, the accumulation-mode MISFET is unlikely to be influenced by a region in the vicinity of the MIS interface where interface state density is high, and thus channel mobility (carrier mobility) is improved.
Normally, as a SiC substrate used for such a semiconductor device, an off substrate whose principal surface is deviated and inclined from a nominal crystal plane (e.g., a (0001) plane) is used. This is because if such an off substrate is used, the high resistance SiC layer 132 is subjected to step flow growth when it is epitaxially grown, and thus the crystallinity of the high resistance SiC layer 132 is improved.